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Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
( ) ( )
P VCC = ? C N × V CC _ 2 × f IN + C P × V CC _ 2 × f IN ? × ( BR F × BTD )
? V
? ?
?
2 ?
? 2 ? ?
P VPP = ? ? ( C O L ) × f IN × ( V PP _ ? V NN _ ) ? + ? PP _ × ? × ( ) ?
+ C
BRF × BTD
? ? ?
2 ? ?
? ?
? ? R L
device. In this case, whenever both the INP_ and INN_
inputs are low and the INC_ input is high, the active
clamp circuit pulls the output to GND through the OCP_
and OCN_ outputs (see Table 1 for more information).
Power-Supply Ramping and
Gate-Source Short Circuit
The MAX4810/MAX4811/MAX4812 include a gate-
source short circuit that is controlled by the enable input
(EN_). When SHDN is high and EN is low, a 60 Ω switch
shorts together the gate and source of the high-side out-
put FET. At the same time, a similar switch shorts the
gate and source of the low-side output FET (Table 1).
The gate-source short circuit prevents accidental turn-
on of the output FETs due to the ramping voltage on
V PP_ and V NN_ , and allows for faster ramping rates and
smaller delay times between pulsing modes.
Shutdown Mode
SHDN is common to both channel 1 and channel 2 and
powers up or down the device. Drive SHDN low to power
down all internal circuits (except the clamp circuits).
When SHDN is low, the device is in the lowest power
state (1μA) and the gate-source short circuit is disabled.
The device takes 1μs (typ) to become active when SHDN
is disabled.
Thermal Protection
A thermal shutdown circuit with a typical threshold of
+150°C prevents damage due to excessive power dis-
sipation. When the junction temperature exceeds T J =
+150°C, all outputs are disabled. Normal operation typ-
ically resumes after the IC’s junction temperature drops
P VNN_ ) must be kept below the maximum power-dissi-
pation limit. See the Typical Operating Characteristics
section for more information on typical supply currents
versus switching frequencies.
The device consumes most of the supply current from
V CC_ supply to charge and discharge internal nodes
such as the gate capacitance of the high-side FET (C P )
and the low-side FET (C N ). Neglecting the small quies-
cent supply current and a small amount of current used
to charge and discharge the capacitances at the inter-
nal gate clamp FETs, the power consumption can be
estimated as follows:
? ?
? ?
f f f
IN = INN + INP
Where f INN and f INP are the switching frequency of the
inputs INN, INP respectively, and where BRF is the
burst repitition frequency and BTD is the burst time
duration. The typical value of the gate capacitances of
the power FET are C N = 0.2nF, C P = 0.4nF.
For an output load that has a resistance of R L and
capacitance of C L , the MAX4810/MAX4811/MAX4812
power dissipation can be estimated as follows (assume
square wave output and neglect the resistance of the
switches):
1
?
below +130°C.
Applications Information
where C O is the output capacitance of the device.
Power Supplies and Bypassing
AC-Coupling Capacitor Selection
The value of all AC-coupling capacitors (between C DP_
and C GP , and between C DN_ and C GN_ ) should be
between 1nF to 10nF. The voltage rating of the capaci-
tor should be at least as high as V PP_ . The capacitors
should be placed as close as possible to the device.
Because INP_ and part of INC_ are AC-coupled to the
output devices, they cannot be driven high indefinitely
when the device is active.
Power Dissipation
The power dissipation of the MAX4810/MAX4811/
MAX4812 consists of three major components caused
by the current consumption from V CC_ , V PP_ , and V NN_ .
The sum of these components (P VCC_ , P VPP_ and
The MAX4810/MAX4811/MAX4812 operate from inde-
pendent supply voltage sets (only V DD and V SS are
common to both channels). The logic input circuit oper-
ates from a +2.7V to +6V single supply (V DD ). The
level-shift driver dual supplies, V CC_ /V EE_ operate from
±4.75V to ±12.6V.
The V PP_ /V NN_ high-side and low-side supplies are dri-
ven from a single positive supply up to +220V, from a
single negative supply up to -200V, or from ±110V dual
supplies. Either V PP_ or V NN_ can be set at 0. Bypass
each supply input to ground with a 0.1μF capacitor as
close as possible to the device.
Depending on the load of the input, additional bypass-
ing may be needed to keep the output of V NN_ and
V PP_ stable during output transitions. For example, with
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